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Interface
The pinout of Figure 42 is a superset of all possible ports. In every configuration only a subset of these is
used.
Table 14 CoreFIR I/O Signals
Signal
In/Out
Port width
Description
expressed in
Bits
DATAI
In
Input data width,
Input data to be filtered.
DATA_WIDTH
DATAI_VALID
In
1
Input data valid. Active high. When the signal is active, the input data sample
is loaded into the FIR filter. DATAI_VALID should not be active, if READY
signal is inactive. Input data samples coming while the READY signal is
inactive are ignored.
COEFI
In
Coefficient bit
width,
Coefficient input. The coefficients are to be loaded sequentially, one by one.
This port is enabled only when Reloadable coefficient mode is selected.
COEF_WIDTH
COEFI_VALID
In
1
Coefficient valid. Active high. When the signal is active, a coefficient is
loaded into the FIR Filter. This port is enabled only when Reloadable
coefficient mode is selected.
COEF_REF
In
1
Refresh coefficients. Active high.
In Reloadable coefficient mode, the signal initiates reloading coefficients into
Auxiliary page of the coefficient storage.
In Multiple constant set mode, the signal starts loading into the Auxiliary page
another set of coefficients pointed to by the input COEF_SEL.
COEF_REF_
DONE
Out
1
Done refreshing coefficients. Active high.
Notifies that reloading coefficients or loading another multiple set into the
auxiliary page is completed. Now the auxiliary page is ready to become the
active one.
COEF_SEL
In
4
Coefficient set selector. Identifies the pre-programmed fixed coefficient set to
be loaded on the Auxiliary page. This port is enabled only when Multiple
coefficients mode is selected.
CLK
NGRST
In
In
1
1
Clock. Rising edge active. The core master clock.
Asynchronous reset. Active low. Resets all internal fabric registers. The
signal is expected to follow the FPGA power-on.
RSTN
In
1
Optional synchronous reset. Active low. Being asserted along with CLK
signal, resets all internal fabric registers.
FIRO
FIRO_VALID
Out
Out
DATA_WIDTH +
COEF_WIDTH +
ceiling(log 2 TAPS)
1
Data output. The filtered data appear on this port. It is a full precision output.
For example, at 12-bit data, 15-bit coefficients, and 150 taps, M = 10 the
output width = 12 + 15 + ceil(log 2 150) = 12 + 15 + 8 = 31 bits.
Output data valid. Active high. Indicates that a new output data sample is
present at the FIRO port.
COEF_ON
In
1
Coefficients on. Active high. Swaps active and auxiliary pages of the
coefficient memory.
In Multiple constant set mode (COEF_TYPE==0, COEF_SETS>1), the signal
replaces the current coefficient set with the one loaded in the Auxiliary page.
In Reloadable coefficient mode (COEF_TYPE == 1) the signal makes the
filter start using coefficients recently loaded in the auxiliary page.
The port is enabled in Multiple set and Reloadable modes. In Constant
coefficient mode (COEF_TYPE==0, COEF_SETS==0), CoreFIR starts using
the coefficients shortly after the FPGA is powered.
CoreFIR v8.5 Handbook
49
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